HoloAudio – May DAC

Single crystal nano fuseSpecification: 5X20mm @2A(220v) or 4A(110v)Withstand voltage: 250V (T) slow speedFeatures:

This product is complicated in process, special materials can not be made, this fuse is 100% pure handmade!

Tip: Input in different directions, the tone is different. Can try different directions.

This fuse structure is relatively complicated, it is handmade, so the cost is not cheap, the structure is crimped, the contacts are firm and reliable, plated 24K gold, non-chemical gold.

The fuse is made of imported single crystal silver-copper alloy.

Fill the fuse with 2 heads of quartz sand for good shock absorption and arc extinguishing. After nano-processing, the inner filling of the quartz sand is filled with nano-graphite, and the graphite has ultra-high conductivity and high anti-interference characteristics.

The sound is beautiful, soothing and strong in layering. This is the flagship product of high-end fuses so far.

In the middle is graphene, which has the advantages of ultra-high conductivity and anti-interference. The fuse is a single crystal silver-copper alloy containing 10% precious metal, treated with nanographene, and stranded with a single crystal silver.The fuse cap is stamped from 99.99% 4N copper, one end is plated with 24K gold and one end is plated with sterling silver.

Increasing the conductivity and the speed of the power supply make the fuse and the socket highly accessible.

The fuse is firmly pressed by a large one and two small caps made of 4N copper. This process protects the fuse in the middle of the fuse. The fuse and the cap are in good contact and the contact is firm, which can prevent the microphone effect.

Reduce the oscillation of current passing, making the sound quality more pure and the image more stable.The inside is filled with two quartz sands, and the middle is filled with nano graphene.

Graphite has super high conductivity, high anti-interference and other characteristics, and the sound is beautiful, soothing and strong. It has great benefits for sound quality and security, but it can only be handmade.

The ceramic tube has anti-resonance and eliminates the effect of the microphone sound.The fuse is made of a single crystal silver-copper alloy, and a very fine single crystal silver wire is wound to correct the sound.

After nano-treatment, it has excellent two-end extension, transient response, dynamic and musical sense.

Fuse Type for L1 and L2 May :

Shurter Gold fuse type

2A SB 5x20mm (220v) and 4A SB 5x20mm (110V)

Modern and popular delta-sigma type DAC differs from R2R within one clock analog value can recover a sampling point, and the delta-sigma is used to represent an analog signal after passing through oversampling and high-speed digital switching 0 and 1.

In comparison, the conversion structure of R2R is most direct and pure, but delta-sigma is essentially a digital chip, high-speed digital signals 0 and 1 switch to the low-pass filter to process the analog signal and this process is prone to various problems, produce digital sound (digititus) and also in the super-sampling process will inevitably cause some ringing and distortion.

But DAC R2R structure requires high-precision resistor network which the cost can be very expensive. And the digital delta-sigma DAC chip in comparison is very low cost. Patented R2R technology. This is the first discrete DAC that has Linear compensation and this allows for ultimate music reproduction accuracy.

Dual R2R ladder network with advanced architecture for PCM, and Dual Resistor Ladder network with optimized architecture for DSD!

I/O stages: There is an Op Amp used for input stage and discrete component used for the output stage. The discrete output stage is working in pure class A.  It’s BiPolar Junction Transistors, direct coupled. 

A common question we get…” Why do you use an Op amp at the input of the DAC?”  

The input stage with an opamp is a good choice. It has a paired transistor input by the nature it is manufactured. But an opamp for the output stage is limited due to it’s size and the thermal capability. Also, no one will offer an opamp with class A output as it’s efficiency is so low. So an opamp used as input and discrete output combined together will have an advantage. It doesn’t mean that all discrete is not good. Actually, if we need to achieve enough low distortion. It needs at least 30-40 transistors. Which not only will it be huge and waste of space but it will also be too costly. I mean, to beat the opamp’s performance, a simple discrete architecture is not possible, although an all discrete design looks beautiful.

We use opamp+discrete architecture for the amp parts of May. Opamp is used for the input stage, discrete is used for the output stage. All the transistors in the opamp are in the same die, then it is matched by nature. This is key because by now, there are few choice for low noise matched pair transistors but an opamp has plenty of them inside. The Output stage is discrete because it generates a bit of heat. We need a class A output stage. So you can see May is very hot compared to other DACs. An opamp output simply can’t handle that power.

The true balanced DUAL MONO circuit design

XLR is using all of the circuit and RCA is just using half of them. The balanced output has better performance (THD, noise) and also better common mode rejection rate. If you’re listening environment contains interference, either from AC power or from EMI/RF then you will find a full balanced system can really help significantly.

Now the May is implemented with femto clocks, and also new discrete ultra high performance voltage regulators.

It has an advanced PLL (phase lock loop) circuit that is completely custom built for ultra high performance anti jitter performance.

Even the highest levels of jitter are near eliminated which delivers world class performance. Using Crystek VXCO clocks that will take any incoming digital signal an reclock it to perfection!

This feature can be enabled or disabled to test and prove it’s performance is truly spectacular. Note: this is NOT an off the shelf PLL, but it’s truly the most powerful PLL found in a DAC. Or at least to our knowledge it’s the most powerful PLL ever...

Spdif usually is a not a good protocol because it’s very old and dated! It was designed in 70s together with CD with Sony and Philips. As you may know, It encodes the data signal together with clock signal so it can be transferred by a one-core cable. It makes the cable easy to source, but to encode the data to clock at the transmit side and decode the clock from data at the receiving side, creates jitter.

Toslink is a fiber glass version of Spdif. So Toslink adds even more jitter while doing electronic to photo and photo to electronic translation. So people will see clearly that I2S is usually better than SPDIF because I2S has 4 separate signal, 3 clocks 1 data. So it does not have encoding-decoding stuff thus has a better jitter performance.

This is important to know this.A common technique to improve the clock signal from SPDIF is PLL. A PLL is to use a local clock generator to track the source clock. You know jitter is actually a time deviation problem. For example, the fist period frequency is 44101Hz and the following second period is 44099Hz. Thus it has 2/44100 jitter. A PLL is to smooth the time deviation of clock. So after the PLL, it can be 44100.9-44099.1(this is a weak/poor performing PLL). Or it can be 44100.1-44099.9(this is a strong performance PLL).

Usually, a SPDIF chip, like AK4118A, has an internal PLL. AK4118A is good chip compared to other Spdif receiver chip and it marks 50ps jitter. It’s the best we can get from a commercial chip. But it’s far from ideal, and definitely not enough for a HiFi standard we are implementing in the May dac. So we need a significantly stronger performing PLL. If the PLL is strong enough, it can smooth the44101-44009 source clock to 44100.00001-44009.99999 (very close to ideal 44100-44100)But to make a stronger PLL is not easy, it’s actually incredibly difficult. First you need a powerful local clock source.

A fixed clock can’t be used because it need to be adjusted to follow source clock rate. A common solution to use a VCO(voltage controlled oscillator). VCO is made by resistors, capacitor and inductors. The cost is low but performance is not so great. So, a better solution is to use VCXO(Voltage controlled crystal oscillator), it uses crystal as oscillator and crystal is a far better oscillator. The VCXO we used in May is Crystek’s CVHD-957. This the best VCXO we can get now.The second hard problem is, the data need to be synchronized with clock.

For example, the source has 44101-44099clock from Spdif, that also mean it has 44101 samples in first period and 44099 samples in second period. So a good local44100-44100 clock will have to throw away one sample in first period and lack one sample in second period.

An easy fix to it is to use digital filter to smooth the data and it calls ASRC, but ASRC actually modified the data. So after ASRC, the data is modified thus not bit perfect anymore. And digital filter can also generate time domain problems like ringing artifacts. So, a digital filter is not a good way to solve this problem, or you can say, it solve a problem by introduce another problem.May uses a fifo buffer to store the extra one sample in first period and release it in second period. So it has no harm to data. The difficulty for this design is how to manage fifo buffer.

It can be a problem when you have a long-term jitter. And long-term jitter is actually called low frequency phase noise in a frequency domain point of view. To explain it easily, let’s take a example, a long term jitter can be like this, 44101-44102-44103-44104-44105-44104-44103-44102-44101-44100-44099-44098-44097-44096-44095-44096-44097-44098-44099-44100. So you see, it will have 25 extra sample in first ten periods, so the fifo buffer need to able store enough of them and release it in next 10 periods.So, as a result, May’s PLL’s corner frequency is set to 0.05-0.1Hz in 3-orders.

Than means it can reduce a 10s long term jitter by 90%, 1s period jitter by 99%, 0.1s period jitter by 99.9%…… That maybe the most powerful PLL in this industrial. And the most important is, it won’t lose data, it can still locking the source while huge jitter comes in.

When you compared other similar PLL in the industrial, you can see it simply unlock the signal when huge jitter comes in. So, in that way, it simply stop you from listening, it tells you there is a problem but not solve it.I have attached 2 pictures. The AP equipment generate huge jitters to SPDIF(750ns, 1KHz).

If the PLL turned off, you will see an very ugly spectrum that means the jitter distorted the analog signal badly. The other picture turn on the PLL, and you can see it beautifully removed almost all the jitters.

Compared to other competitors PLL. They won’t remove the jitter so clean, and simply unlock the signal for more than 10ns jitters.